Semiconductor devices and methods for manufacturing the same

ABSTRACT

Certain embodiments relate to semiconductor devices having an improved dielectric strength and methods for manufacturing the same. A semiconductor device  1000  may have a field effect transistor  100.  The field effect transistor  100  includes a gate dielectric layer  30,  a source region  32  and a drain region  34.  A first semi-recessed LOCOS layer  40  may be formed between the gate dielectric layer  30  and the drain region  34.  A second semi-recessed LOCOS layer  50  may be formed between the gate dielectric layer  30  and the source region  32.  A first offset impurity layer  42  may be formed below the first semi-recessed LOCOS layer  40.  A second offset impurity layer  52  may be formed below the second semi-recessed LOCOS layer  50

TECHNICAL FIELD

[0001] The present invention relates to semiconductor devices andmethods for manufacturing the same, including semiconductor deviceshaving an improved dielectric strength and methods for manufacturing thesame.

RELATED ART

[0002] Presently, there is known a field effect transistor having aLOCOS (Local Oxidation Of Silicon) offset structure, which is a fieldeffect transistor having an improved dielectric strength. A field effecttransistor having a LOCOS offset structure is a transistor in which aLOCOS layer is provided between a gate dielectric layer and a drainregion, wherein an offset impurity layer is formed below the LOCOSlayer. For example, Japanese patent No. 2705106 and Japanese patent No.2534508 describe field effect transistors having LOCOS offset structure.

[0003] It is noted that a field effect transistor having a LOCOS offsetstructure has a problem in which a bird's beak is formed at an end ofthe LOCOS such that the active region is narrowed.

SUMMARY

[0004] One embodiment relates to a semiconductor device including afield effect transistor, the field effect transistor including a gatedielectric layer, a source region and a drain region. A firstsemi-recessed LOCOS layer is provided between the gate dielectric layerand the drain region, and a second semi-recessed LOCOS layer is providedbetween the gate dielectric layer and the source region. A first offsetimpurity layer is provided below the first semi-recessed LOCOS layer,and a second offset impurity layer is provided below the secondsemi-recessed LOCOS layer.

[0005] Another embodiment relates to a method for manufacturing asemiconductor device including a field effect transistor, the fieldeffect transistor including a gate dielectric layer, a source region anda drain region. A first semi-recessed LOCOS layer is provided betweenthe gate dielectric layer and the drain region, and a secondsemi-recessed LOCOS layer is provided between the gate dielectric layerand the source region. A first offset impurity layer is provided belowthe first semi-recessed LOCOS layer, and a second offset impurity layeris provided below the second semi-recessed LOCOS layer. The methodincludes forming a first recessed section in a region where the firstsemi-recessed LOCOS layer is to be formed, and forming a second recessedsection in a region where the second semi-recessed LOCOS layer is to beformed. The method also includes implanting an impurity in asemiconductor substrate in the first recessed section and in the secondrecessed section. The method also includes thermally oxidizing thesemiconductor substrate to form the first semi-recessed LOCOS layer inthe first recessed section and to form the second semi-recessed LOCOSlayer in the second recessed section.

[0006] Another embodiment relates to a semiconductor device includingfirst and second field effect transistors, each including a gatedielectric layer and source and drain regions. The first and secondfield effect transistors also each include a first semi-recessed LOCOSlayer positioned between the gate dielectric layer and the drain region,and a second semi-recessed LOCOS layer positioned between the gatedielectric layer and the source region. The first and second fieldeffect transistors also each include a first offset impurity layer belowthe first semi-recessed LOCOS layer, and a second offset impurity layerbelow the second semi-recessed LOCOS layer. The semiconductor devicealso includes an element isolation region located between the first andsecond field effect transistors.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the invention are described with reference to theaccompanying drawings which, for illustrative purposes, are schematicand not necessarily drawn to scale.

[0008]FIG. 1 schematically shows a semiconductor device in accordancewith a first embodiment of the present invention.

[0009]FIG. 2 schematically shows a cross-sectional view in amanufacturing process in accordance with a second embodiment.

[0010]FIG. 3 schematically shows a cross-sectional view in themanufacturing process in accordance with the second embodiment.

[0011]FIG. 4 schematically shows a cross-sectional view in themanufacturing process in accordance with the second embodiment.

[0012]FIG. 5 schematically shows a cross-sectional view in themanufacturing process in accordance with the second embodiment.

[0013]FIG. 6 schematically shows a cross-sectional view in themanufacturing process in accordance with the second embodiment.

[0014]FIG. 7 schematically shows a cross-sectional view in themanufacturing process in accordance with the second embodiment.

[0015]FIG. 8 schematically shows a cross-sectional view in themanufacturing process in accordance with the second embodiment.

[0016]FIG. 9 schematically shows an enlarged cross-sectional view of arecessed section to describe a main portion in the method formanufacturing a semiconductor device in accordance with the thirdembodiment of the present invention.

DETAILED DESCRIPTION

[0017] Certain embodiments of the present invention relate tosemiconductor devices having an improved dielectric strength and methodsfor manufacturing the same.

[0018] A semiconductor device in accordance with certain embodiments ofthe present invention may include a semiconductor having a field effecttransistor, the field effect transistor including a gate dielectriclayer, a source region and a drain region, wherein a first semi-recessedLOCOS layer is provided between the gate dielectric layer and the drainregion, a second semi-recessed LOCOS layer is provided between the gatedielectric layer and the source region, a first offset impurity layer isprovided below the first semi-recessed LOCOS layer, and a second offsetimpurity layer is provided below the second semi-recessed LOCOS layer.

[0019] In accordance with certain embodiments, for example, thefollowing effects may be attained. The field effect transistor has afirst semi-recessed LOCOS layer and a second semi-recessed LOCOS layer.Further, a first offset impurity layer and the second offset impuritylayer are provided below the first semi-recessed LOCOS layer and thesecond semi-recessed LOCOS layer, respectively. Accordingly, the offsetimpurity layers can be made relatively deep with respect to the channelregion compared to the case where semi-recessed LOCOS layers are notformed. As a result, when the field effect transistor is an ON state,deep depletion layers can be formed by the offset impurity layers.Consequently, the electric field adjacent the drain electrode isalleviated, to thereby increase the drain dielectric strength.

[0020] Also, in accordance with certain embodiments, the width of abird's beak can be narrowed compared to the LOCOS layer. As a result, aminiaturization can be achieved compared to the LOCOS.

[0021] Also, in accordance with certain embodiments, the semiconductordevice may preferably be used as a semiconductor device having a draindielectric strength of 10 -50 V. Also, in particular, the semiconductordevice may preferably be used as a high dielectric strength liquidcrystal display (LCD) driver.

[0022] The semi-recessed LOCOS layer may have a thickness of 0.3-0.7 μm,for example.

[0023] The semiconductor device may preferably have an element isolationregion, and the element isolation region may preferably have asemi-recessed LOCOS structure. When the element isolation region has asemi-recessed LOCOS structure, the element isolation region may beformed in the same process in which the first and second semi-recessedLOCOS layers are formed. A channel stopper layer may be provided belowthe element isolation region.

[0024] A low concentration impurity layer having the same conductivitytype as that of the drain region may preferably be provided around thedrain region. By providing the low concentration impurity layer, whenthe field effect transistor is an ON state, the region of the lowconcentration impurity layer becomes a depletion layer to therebyincrease the drain dielectric strength.

[0025] A semiconductor device in accordance with certain embodiments ofthe present invention can be manufactured, for example, in the followingmanner.

[0026] A method for manufacturing a semiconductor device in accordancewith certain embodiments of the present invention relates to a methodfor manufacturing a semiconductor device having a field effecttransistor, the field effect transistor including a gate dielectriclayer, a source region and a drain region, wherein a first semi-recessedLOCOS layer is provided between the gate dielectric layer and the drainregion, a second semi-recessed LOCOS layer is provided between the gatedielectric layer and the source region, a first offset impurity layer isprovided below the first semi-recessed LOCOS layer, and a second offsetimpurity layer is provided below the second semi-recessed LOCOS layer.The method for manufacturing a semiconductor device in accordance withcertain embodiments includes the steps of:

[0027] (a) forming a first recessed section in a region where the firstsemi-recessed LOCOS layer is to be formed, and forming a second recessedsection in a region where the second semi-recessed LOCOS layer is to beformed

[0028] (b) implanting an impurity in a semiconductor substrate in thefirst recessed section and in the recessed section; and

[0029] (c) thermally oxidizing the semiconductor substrate to form thefirst semi-recessed LOCOS layer in the first recessed section and toform the second semi-recessed LOCOS layer in the second recessedsection.

[0030] The method may further include the step (d) of forming ananti-oxidation layer having a predetermined pattern, wherein the step(c) may preferably be conducted using the anti-oxidation layer formed onthe semiconductor substrate as a mask.

[0031] As a result, the semiconductor substrate in a predeterminedregion can be securely thermally oxidized. Also, in the step (b), whenthe impurity is implanted in the semiconductor substrate, the impurityis suppressed from being implanted in the semiconductor substrate thatis covered by the anti-oxidation layer.

[0032] The anti-oxidation layer may preferably have a film thickness of50-70 nm. When the film thickness of the anti-oxidation layer is 50 nmor greater, when the impurity is implanted in the semiconductorsubstrate in the step (b), the impurity is prevented or inhibited frombeing implanted in the semiconductor substrate that is covered by theanti-oxidation layer.

[0033] Prior to the step (b), the step (e) of forming a protection layerover the semiconductor substrate in the first recessed section and thesecond recessed section may preferably be included. It is noted that theprotection film is a film that suppresses damages to the semiconductorsubstrate when the impurity is implanted in the semiconductor substrate.By the inclusion of the step (e), damage to the semiconductor substratein the first and second recessed sections can be suppressed.

[0034] The protection-layer may, for example, be a silicon oxide layer.The silicon oxide layer may be formed by a thermal oxidation method. Bythe thermal oxidation method, the silicon oxide layer can be securelyformed over an exposed surface of the semiconductor substrate in thefirst recessed section and the second recessed section.

[0035] Also, when the protection film is formed, the step (f) ofremoving the protection film may preferably be included after the step(b). By the inclusion of the step (f), the film quality of thesemi-recessed LOCOS layers thus obtained can be improved.

[0036] In the step (a), each of the first recessed section and thesecond recessed section may preferably be formed with a taperedconfiguration. As a result, in the step (b), the impurity can be readilyimplanted on side surfaces of the silicon substrate in the first andsecond recessed sections.

[0037] The first recessed section and the second recessed section maypreferably have a tapered angle of 60 degrees or greater but preferablyless than 90 degrees. As a result, in the step (b), the impurity can bereadily implanted on side surfaces of the silicon substrate in the firstand second recessed sections.

[0038] In the step (b), an implanting direction of the impurity maypreferably traverse a normal line of a surface of the semiconductorsubstrate. As a result, in the step (b), the impurity can be readilyimplanted on side surfaces of the silicon substrate in the first andsecond recessed sections.

[0039] The implanting direction of the impurity and the normal line ofthe surface of the semiconductor substrate may preferably define anangle that is greater than zero degrees but preferably 45 degrees orless. As a result, in the step (b), the impurity can be readilyimplanted on side surfaces of the silicon substrate in the first andsecond recessed sections.

[0040] Preferred embodiments of the present invention are describedbelow with reference to the accompanying figures.

[0041] A semiconductor device in accordance with a first embodiment ofthe present invention is described below. FIG. 1 schematically shows across-sectional view of a semiconductor device in accordance with thefirst embodiment of the present invention.

[0042] A semiconductor device 1000 includes element isolation regions20. The element isolation regions 20 each have a semi-recessed LOCOSstructure. A field effect transistor (herein below referred to as“transistor”) 100 may be provided for each region defined by the elementisolation regions 20.

[0043] The transistor 100 includes a gate dielectric layer 30, a sourceregion 32, and a drain region 34. The source region 32 and the drainregion 34 are each formed from an N₊-type impurity diffusion layerformed in a P-type well in the case of an N-type transistor as anexample; and are each formed from a P₊-type diffusion layer formed in anN-type well in the case of a P-type transistor as an example.

[0044] First and second semi-recessed LOCOS layers 40 and 50 may beformed in a manner continuous with the gate dielectric layer 30. Moreconcretely, the first semi-recessed LOCOS layer 40 is formed between thegate dielectric layer 30 and the drain region 34, and the secondsemi-recessed LOCOS layer 50 is formed between the gate dielectric layer30 and the source region 32. The film thickness of the first and secondsemi-recessed LOCOS layers 40 and 50 may vary depending on the devicedesigns, and may be, for example, 0.3-0.7 μm, and more preferably,0.4-0.6 μm. First and second offset impurity layers 42 and 52 are formedbelow the first and second semi-recessed LOCOS layer 40 and 50,respectively. The first and second offset impurity layers 42 and 52 areeach formed from an N-type impurity diffusion layer in the case of anN-type transistor as an example; and is formed from a P-type diffusionlayer in the case of a P-type transistor as an example.

[0045] A channel stopper layer 60 may be formed in a central area of andbelow the element isolation region 20. The channel stopper layer 60 isformed from a P-type impurity diffusion layer in the case of an N-typetransistor as an example; and is formed from an N-type diffusion layerin the case of a P-type transistor as an example.

[0046] Low concentration impurity layers 62 are formed below endsections of the element isolation region 20 adjacent to the drainregions 34. By the low concentration impurity layers 62, when thetransistor is an ON state, the region of the low concentration impuritylayers 62 becomes depletion layers such that the drain dielectricstrength can be increased. The low concentration impurity layers 62 areeach formed from an N-type impurity diffusion layer in the case of anN-type transistor as an example; and formed from a P-type diffusionlayer in the case of a P-type transistor as an example.

[0047] A contact region is formed in the semiconductor device 1000 toapply a voltage to the silicon substrate 10. The contact region isisolated from the source region or the drain region by the elementisolation region. A channel stopper layer can be formed below theelement isolation region depending on the requirements.

[0048] An interlayer dielectric layer 70 is formed over the siliconsubstrate 10. Contact holes 72 are formed in specified regions of theinterlayer dielectric layer 70. Wiring layers 74 are formed in thecontact holes 72 and over the interlayer dielectric layer 70.

[0049] The semiconductor device 1000 in accordance with the firstembodiment of the present invention may have one or more of the effectsdescribed below.

[0050] (a) In the present embodiment, each of the transistors 100 hasthe semi-recessed LOCOS layers 40 and 50. Also, the offset impuritylayers 42 and 52 are provided below the semi-recessed LOCOS layers 40and 50. Therefore, the offset impurity layers 42 and 52 can be maderelatively deep with respect to the channel region compared to the casewhere any semi-recessed LOCOS layer is not formed. As a result, when thetransistor is an ON state, a deep depletion layer can be formed by theoffset impurity layers 42 and 52. Consequently, the electric fieldadjacent the drain electrode is alleviated, such that the draindielectric strength is increased.

[0051] (b) Furthermore, the semiconductor device may preferably be usedas a semiconductor device having a drain dielectric strength of 10-50 V.Also, in particular, the semiconductor device may preferably be used asa high dielectric strength liquid crystal display (LCD) driver.

[0052] A method for manufacturing a semiconductor device in accordancewith a second embodiment of the present invention is described below.More particularly, taking an N-type transistor as an example, a processfor manufacturing a semiconductor device is described.

[0053] FIGS. 2-8 schematically show cross-sectional views in amanufacturing process in accordance with the second embodiment.

[0054] (1) First, as shown in FIG. 2, a silicon oxide nitride layer 80is formed over a silicon substrate 10 by a CVD method. The silicon oxidenitride layer 80 has a film thickness of, for example, 8 to 12 nm. Then,a silicon nitride layer 82 is formed over the silicon oxide nitridelayer 80 by a CVD method. The silicon nitride layer 82 may have any filmthickness to the extent that it can prevent ions from being implanted inthe silicon substrate 10 that is covered by the silicon nitride layer 82in an ion implementation step to be described below. The film thicknessof the silicon nitride layer 82 may preferably be 50-70 nm, and morepreferably 60-65 nm.

[0055] (2) Then, as shown in FIG. 3(a), a first resist layer R1 having apredetermined pattern is formed over the silicon nitride layer 82. Thefirst resist layer R1 has openings above regions where element isolationregions 20 and first and second semi-recessed LOCOS layers 40 and 50 areto be formed.

[0056] Then, the silicon nitride layer 82, the silicon oxide nitridelayer 80 and the silicon substrate 10 are etched using the first resistlayer R1 as a mask. As a result, first through third recessed (or trenchor concave) sections 84 a, 84 b and 84 c are formed in regions where theelement isolation regions 20 and the first and second semi-recessedLOCOS layers 40 and 50 are to be formed. Recessed section refers to anopening including, but not limited to, a concave opening or trench. Thefirst recessed section 84 a is formed in a region that becomes the firstsemi-recessed LOCOS layer 40, the second recessed section 84 b is formedin a region that becomes the second semi-recessed LOCOS layer 50, andthe third recessed section 84 c is formed in a region that becomes theelement isolation region 20. It is noted that FIG. 3(b) schematicallyshows an enlarged cross-sectional view of the first recessed section 84a of FIG. 3(a). The width W10 of the first recessed section 84 a maydiffer depending on the dielectric strength and characteristics of thedevice, and may be, for example, 0.3-5.0 μm, and more preferably,0.5-2.0 μm. The depth D10 of the first recessed section 84 a may differdepending on the dielectric strength and characteristics of the device,and may be, for example, 0.05-0.15 μm, and more preferably, 0.08-0.1 μm.The width and the depth of the second recessed section 84 b may be thesame as those of the first recessed section 84 a. The depth of the thirdrecessed section 84 c may be the same as that of the first recessedsection 84 a. Then, the first resist layer R1 is removed.

[0057] (3) Then, as shown in FIG. 4(a), a silicon oxide layer 90 isformed over an exposed surface of the silicon substrate 10 by a thermaloxidation method. It is noted that FIG. 4(b) schematically shows anenlarged cross-sectional view of the first recessed section 84 a of FIG.4(a). It is noted that the silicon oxide layer 90 can be formed by a CVDmethod. The film thickness of the silicon oxide layer 90 may be, forexample, 5.0-10 nm, and more preferably, 6.0-7.0 nm.

[0058] (4) Then, as shown in FIG. 5(a), a second resist layer R2 havinga predetermined pattern is formed. The second resist layer R2 hasopenings provided above the first recessed sections 84 a and the secondrecessed sections 84 b, and end sections of the third recessed sections84 c. More concretely, the openings are provided above regions where thefirst and second semi-recessed LOCOS layers 40 and 50 and the lowconcentration impurity layers 62 are to be formed.

[0059] Then, N-type ions 92 a are implanted in the silicon substrate 10using the second resist layer R2 as a mask. As a result, N-type impuritydiffusion layers 92 are formed in the first through third recessedsections 84 a, 84 b and 84 c. In succeeding steps, the N-type impuritydiffusion layers 92 in the first and second recessed sections 84 a and84 b become first and second offset impurity layers 42 and 52,respectively. Also, the N-type impurity diffusion layers 92 in the thirdrecessed sections 84 c become low concentration impurity layers 62.

[0060] It is noted that FIG. 5(b) schematically shows an enlargedcross-sectional view of the first recessed section 84 a of FIG. 5(a).Because the silicon oxide layer 90 is formed, damage by the ionimplantation to the silicon substrate 10 in the first though thirdrecessed sections 84 a, 84 b and 84 c are suppressed. As a result,crystal lattices of the silicon substrate 10 are severed such that theformation of electrical current paths is suppressed. The N-type ions 92a may be, for example, phosphorous ions. The ion acceleration voltagemay vary depending on the dielectric strength and characteristics of thedevice, and may be, for example, 10-50 keV, and more preferably 20-25keV. The dose may vary depending on the dielectric strength andcharacteristics of the device, and may be, for example, 1.0E+13 to1.5E+14 cm⁻², and more preferably, 3.0E+13 to 5.0E+13 cm⁻². The ionimplantation angle (an angle defined between a normal line L1 of thesurface of the semiconductor substrate and a direction in which the ionsare implanted) θ is not particularly limited, and may be, for example,0-45 degrees, and more preferably, greater than zero (0) degrees but 45degrees or less, and even more preferably, between 5 degrees and 20degrees. When the ion implantation angle θ is greater than zero (0)degrees but 45 degrees or smaller, the ions can be securely implanted inthe side surfaces of the silicon substrate 10 in the recessed sections84 a, 84 b and 84 c. Then, the second resist layer R2 is removed.

[0061] (5) Then, as shown in FIG. 6, a third resist layer R3 having apredetermined pattern is formed. The third resist layer R3 has anopening provided in a central section of the third recessed section 84c. More concretely, the third resist layer R3 has the opening providedabove a region where the channel stopper layer 60 is to be formed.

[0062] Then, P-type ions 94 a are implanted in the silicon substrate 10using the third resist layer R3 as a mask. As a result, P-type impuritydiffusion layers 94 are formed in the third recessed sections 84 c. Insucceeding steps, the P-type impurity diffusion layers 94 become channelstopper layers 60. The P-type ions 94 a may be, for example, boron ions.The ion acceleration voltage may vary depending on the dielectricstrength and characteristics of the device, and may be, for example,5-10 keV, and more preferably 7-8 keV. The dose may vary depending onthe dielectric strength and characteristics of the device, and may be,for example, 1.0E+13 to 1.5E+14 cm⁻², and more preferably, 3.0E+13 to1.0E+14 cm⁻². Then, the third resist layer R3 is removed.

[0063] (6) Then, as shown in FIG. 7(a), the silicon oxide layer 90 isremoved. It is noted that FIG. 7(b) schematically shows an enlargedcross-sectional view of the first recessed section 84 a of FIG. 7(a). Itis noted that the silicon oxide layer 90 may not have to be removed ifit does not adversely affect the characteristics of the device.

[0064] Then, the silicon substrate 10 is thermally oxidized using thesilicon nitride layer 82 as an anti-oxidation layer. As a result, asshown in FIG. 8, the element isolation regions 20 and the first andsecond semi-recessed LOCOS layers 40 and 50 are formed. In this thermaloxidation step, the ions implanted in the silicon substrate 10 in thefirst and second recessed sections 84 a and 84 b are defused (drivenin), such that first and second offset impurity layers 42 and 52 areformed. Also, at the same time, the ions implanted in the siliconsubstrate 10 in the third recessed sections 84 c are defused (drivenin), such that channel stopper layers 60 and low concentration impuritylayers 62 are formed.

[0065] Then, the silicon nitride layer 82 and silicon oxide nitridelayer 80 are removed. Then, the surface of the silicon substrate 10 isthermally oxidized to form gate dielectric layers 30.

[0066] (7) Next, as shown in FIG. 1, a conductive polysilicon layer isdeposited over the wafer including the LOCOS layers 20. Next, byconducting photolithography and etching, gate electrodes 36 are formedover the gate dielectric layers 30. Then, sidewalls may be formed on thesides of the gate electrodes 36 depending on the requirements.

[0067] Then, phosphorus ions are implanted using the gate electrodes 36and the first and second semi-recessed LOCOS layers 40 and 50 as a maskto form source/drain regions 32, 34 of an N-channel transistor.

[0068] Then, an interlayer dielectric layer 70 is deposited over thewafer including the gate electrodes 36. By conducting photolithographyand etching, contact holes 72 are formed in the interlayer dielectriclayer 70.

[0069] Then, a conduction layer formed from, for example, an aluminumalloy, copper, or the like is deposited in the contact holes 72 and overthe interlayer dielectric layer 70; and the conduction layer ispatterned to form wiring layers 74.

[0070] The method for manufacturing the semiconductor device inaccordance with the second embodiment of the present invention may haveone or more of the effects described below.

[0071] (a) In accordance with the present embodiment, when implantingions in the recessed sections 84 a, 84 b and 84 c, the silicon oxidelayer 90 is formed over the surface of the silicon substrate 10 in therecessed sections 84 a, 84 b and 84 c. As a result, damages by the ionimplantation to the silicon substrate 10 in the recessed sections 84 a,84 b and 84 c are suppressed. As a result, crystal lattices of thesilicon substrate 10 are severed such that the formation of electricalcurrent paths is suppressed.

[0072] (b) In the step of implanting ions in the silicon substrate 10 inthe first and second recessed sections 84 a and 84 b, when the ionimplantation angle θ is greater than zero (0) degrees but 45 degrees orless, the following effects may be achieved. Namely, when the ionimplantation angle θ is greater than zero (0) degrees but 45 degrees orless, the ions can be securely implanted on sides of the siliconsubstrate 10 in the first and second recessed sections 84 a and 84 b. Asa result, the first and second offset impurity layers 42, 52 can besecurely formed on the sides of the first and second semi-recessed LOCOSlayers 40 and 50.

[0073] It is noted that, P-type transistors can be manufactured inparallel with the manufacturing of the N-type transistors. For example,P-type transistors can be manufactured in parallel with themanufacturing of the N-type transistors in the following manner.

[0074] (A) Recessed sections in regions where offset impurity layers ofthe P-type transistors are to be formed may be formed at the same timewhen the above-described recessed sections are formed in the formingstep (2). (B) The step of implanting P-type ions to form the offsetimpurity layers of the P-type transistors may be conducted at the sametime when the step (5) to form the above-described channel stopperlayers is conducted.

[0075] Next, a method for manufacturing a semiconductor device inaccordance with a third embodiment of the present invention is describedbelow. FIG. 9 schematically shows an enlarged cross-sectional view of arecessed section to describe a main portion in the method formanufacturing a semiconductor device in accordance with the thirdembodiment of the present invention.

[0076] The third embodiment is different from the second embodiment inthe method of forming recessed sections. The third embodiment is thesame as the second embodiment except the method of forming recessedsections, and therefore a detailed description thereof is omitted.

[0077] In the third embodiment, as shown in FIG. 9, the siliconsubstrate 10 is etched in a manner that the first and second recessedsections 84 a and 84 b each have a tapered configuration. The taperangle α of the recessed section is less than 90 degrees, morepreferably, 60 degrees or greater but less than 90 degrees, and evenmore preferably between 70 and 80 degrees. An etching method for formingthe recessed sections may not particularly be limited as long as themethod can provide the first and second recessed sections 84 a withtapered shapes. More concretely, the silicon substrate 10 may be etchedby an etching apparatus having parallel plate electrodes in thefollowing manner as an example.

[0078] First, the silicon substrate 10 is disposed over the parallelplate lower electrode. Power of, for example, 200 W may be appliedbetween the electrodes to etch the silicon substrate 10. As a concretecondition, the etching is conducted under a vacuum having a pressure of,for example 700 mTorr. An etching gas to be used in the etching may be agas including, for example, CHF₃, CF₄, Ar, O₂, and the quantity ratio ofthese gases may be, for example, 10/70/800/4 sccm (═CHF₃/CF₄/Ar/O₂).

[0079] The method for manufacturing the semiconductor device inaccordance with the third embodiment of the present invention mayinclude one or more of the effects described below.

[0080] (a) The third embodiment may provide a similar effect as theeffect (a) of the second embodiment.

[0081] (b) In the third embodiment, the recessed sections 84 a and 84 bare formed to have tapered configurations (the taper angle α is lessthan 90 degree). As a result, in a step of implanting ions in thesilicon substrate 10 in the recessed sections 84 a and 84 b, the ionscan be securely implanted in the sides of the second substrate 10. As aresult, the first and second offset impurity layers 42 and 52 can besecurely formed on the sides of the first and second semi-recessed LOCOSlayers 40 and 50.

[0082] The present invention is not limited to the embodiments describedabove, and a variety of other embodiments can be made within the scopeof the subject matter of the invention.

What is claimed:
 1. A semiconductor device comprising a field effecttransistor, the field effect transistor including a gate dielectriclayer, a source region and a drain region, wherein a first semi-recessedLOCOS layer is provided between the gate dielectric layer and the drainregion, a second semi-recessed LOCOS layer is provided between the gatedielectric layer and the source region, a first offset impurity layer isprovided below the first semi-recessed LOCOS layer, and a second offsetimpurity layer is provided below the second semi-recessed LOCOS layer.2. A semiconductor device according to claim 1, wherein the firstsemi-recessed LOCOS layer and the second semi-recessed LOCOS layer eachhave a thickness of 0.3-0.7 μm.
 3. A semiconductor device according toclaim 1, further comprising an element isolation region, wherein theelement isolation region has a semi-recessed LOCOS structure.
 4. Asemiconductor device according to claim 3, wherein a channel stopperlayer is provided below the element isolation region.
 5. A semiconductordevice according to claim 1, wherein a low concentration impurity layerhaving a conductivity type identical with conductivity type of the drainregion is provided adjacent to the drain region.
 6. A method formanufacturing a semiconductor device comprising a field effecttransistor, the field effect transistor including a gate dielectriclayer, a source region and a drain region, wherein a first semi-recessedLOCOS layer is provided between the gate dielectric layer and the drainregion, a second semi-recessed LOCOS layer is provided between the gatedielectric layer and the source region, a first offset impurity layer isprovided below the first semi-recessed LOCOS layer, and a second offsetimpurity layer is provided below the second semi-recessed LOCOS layer,the method comprising: forming a first recessed section in a regionwhere the first semi-recessed LOCOS layer is to be formed, and forming asecond recessed section in a region where the second semi-recessed LOCOSlayer is to be formed implanting an impurity in a semiconductorsubstrate in the first recessed section and in the second recessedsection; and thermally oxidizing the semiconductor substrate to form thefirst semi-recessed LOCOS layer in the first recessed section and toform the second semi-recessed LOCOS layer in the second recessedsection.
 7. A method for manufacturing a semiconductor device accordingto claim 6, further comprising forming an anti-oxidation layer having apredetermined pattern, wherein the thermally oxidizing the semiconductorsubstrate to form the first semi-recessed LOCOS layer in the firstrecessed section and to form the second semi-recessed LOCOS layer in thesecond recessed section is conducted using the anti-oxidation layerformed on the semiconductor substrate as a mask.
 8. A method formanufacturing a semiconductor device according to claim 7, wherein theanti-oxidation layer has a film thickness of 50-70 nm.
 9. A method formanufacturing a semiconductor device according to claim 7, furthercomprising, before the forming of the anti-oxidation layer, forming aprotection film over the semiconductor substrate in the first recessedsection and in the second recessed section.
 10. A method formanufacturing a semiconductor device according to claim 9, wherein theprotection film is a silicon oxide layer.
 11. A method for manufacturinga semiconductor device according to claim 10, wherein the silicon oxidelayer is formed by a thermal oxidation method.
 12. A method formanufacturing a semiconductor device according to claim 9, furthercomprising, after the implanting an impurity in the semiconductorsubstrate in the first recessed section and in the second recessedsection, removing the protection film.
 13. A method for manufacturing asemiconductor device according to claim 6, wherein the first recessedsection and the second recessed section each are formed in a taperedconfiguration.
 14. A method for manufacturing a semiconductor deviceaccording to claim 13, wherein a tapered angle of each of the firstrecessed section and the second recessed section is 60 degrees orgreater less than 90 degrees.
 15. A method for manufacturing asemiconductor device according to claim 6, wherein an implantingdirection of the impurity traverses a normal line of a surface of thesemiconductor substrate during the implanting an impurity in thesemiconductor substrate in the first recessed section and in the secondrecessed section.
 16. A method for manufacturing a semiconductor deviceaccording to claim 15, wherein the implanting direction of the impurityand the normal line of the surface of the semiconductor substrate definean angle that is greater than zero degrees and no greater than 45degrees.
 17. A semiconductor device comprising: first and second fieldeffect transistors each including a gate dielectric layer; source anddrain regions; a first semi-recessed LOCOS layer positioned between thegate dielectric layer and the drain region; a second semi-recessed LOCOSlayer positioned between the gate dielectric layer and the sourceregion; a first offset impurity layer below the first semi-recessedLOCOS layer; and a second offset impurity layer below the secondsemi-recessed LOCOS layer; and an element isolation region locatedbetween the first and second field effect transistors.
 18. Asemiconductor device according to claim 17, wherein said elementisolation region includes a semi-recessed LOCOS structure.
 19. Asemiconductor device according to claim 17, further comprising a channelstopper layer formed below the element isolation region.
 20. A liquidcrystal display driver comprising the semiconductor device of claim 17.